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microcomputer components 8-bit cmos microcontroller c505l data sheet 06.99 ds 1 http://www.infineon.com/
for questions on technology, delivery and prices please contact the infineon technologies offices in germany or the infineon technologies companies and representatives worldwide: see our webpage at http://www.infineon.com. enhanced hooks technology tm is a trademark and patent of metalink corporation licensed to siemens. c505l data sheet revision history: original version: 06.99 previous releases: page (new version) page (prev. version) subjects (changes since last revision) -- - -- - edition 06.99 published by infineon technologies ag i. gr., st.-martin-strasse 53 d-81541 mnchen ? infineon technologies ag 1999 all rights reserved. attention please! the information herein is given to describe certain components and shall not be considered as warranted characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. infineon technologiesis an approved cecc manufacturer. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office in germany or our infineon technologies representatives worldwide (see address list). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please cont act your nearest in?neon technologies of?ce. in?neon technologies components may only be used in life-support devices or systems with the express written approval of in?neon tech- nologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
data sheet 1 06.99 8-bit cmos microcontroller advance information c505l features ? fully compatible with the standard 8051 microcontroller ? superset of the 8051 architecture with 8 datapointers ? up to 20 mhz operating frequency C 375 ns instruction cycle time @ 16 mhz C 300 ns instruction cycle time @ 20 mhz (50% duty cycle) ? program memory C 32k bytes of on-chip otp memory C externally expandable up to 64 kbytes ? 256-byte on-chip ram ? 256-byte on-chip xram ? five 8-bit and one 6-bit digital i/o ports (port 5 with 6 bits only) C port 1 with mixed analog/digital i/o capability C port 3 with 2 lcd output lines as secondary functions C port 4 and 5 with 8 and 6 lcd output lines respectively as secondary functions (more features are on next page) figure 1 c505l functional units 8 digit. i / o 8 analog inputs / mcb03832 on-chip emulation support module port 4 port 3 port 2 port 1 port 0 8 digit. i / o 8 digit. i / o 2 lcd outputs / real-time clock timer 2 10-bit adc t 0 t 1 oscillator watchdog watchdog timer cpu 8 datapointers 128-segment lcd control xram 256 x 8 256 x 8 ram 8-bit usart port 5 otp 32k x 8 (c505l-4e only) 4-channel pwm 8 digit. i / o 8 digit. i / o 8 lcd outputs / 6 digit. i / o 6 lcd outputs / 20 lcd outputs otp 32k x 8
c505l data sheet 2 06.99 features (contd): ? three 16-bit timers/counters C timer 0 / 1 (c501 compatible) C timer 2 with 4 channels for 16-bit capture/compare operation ? 128-segment lcd controller C 1/4 duty cycle drive C 4 row and 32 column outputs C on-chip programmable reference voltage generation C 20 dedicated lcd output lines (4 rows + 16 columns) ? real-time clock C 47-bit digital clock counter C input frequency of 32.768 khz required C operates in a special power down mode ? full duplex serial interface with programmable baudrate generator (usart) ? 10-bit a/d converter with 8 multiplexed inputs ? twelve interrupt sources with four priority levels ? on-chip emulation support logic (enhanced hooks tm 1) ) ? programmable 15-bit watchdog timer ? oscillator watchdog ? fast power-on reset ? power-saving modes C slow-down mode C idle mode (can be combined with slow-down mode) C 3 special power down modes C software power-down mode with wake up capability through int0 pin or real-time clock ? p-mqfp-80 package ? temperature ranges: sab-c505l t a = 0 to 70 c saf-c505l t a = C 40 to 85 c sak-c505l t a =C40to125 c (max. operating frequency: 12 mhz) ordering information the ordering code for infineon technologies microcontrollers provides an exact reference to the required product. this ordering code identifies: ? the derivative itself, i.e. its function set ? the specified temperature rage ? the package and the type of delivery for the available ordering codes for the c505l please refer to the product information microcontrollers , which summarizes all available microcontroller variants. 1 enhanced hooks technology is a trademark and patent of metalink corporation licensed to infineon technologies.
c505l data sheet 3 06.99 figure 2 logic symbol agnd aref v v ea psen reset ale xtal2 xtal1 8-bit digital i / o 8-bit digital i / o 8-bit digital i / o port 4 port 2 3 port port 8-bit digital i / o / 8-bit digital i / o 1 port 0 port v ss v dd c505l mcl03833 8-bit analog inputs r3 xtal4 xtal3 r0 c31 c0 port 6-bit digital i / o 5
c505l data sheet 4 06.99 figure 3 pin configuration p-mqfp-80 package (top view) p2.0 / ad8 p2.1 / ad9 p2.3 / ad11 p2.2 / ad10 xtal3 p2.7 / ad15 ale psen xtal2 ea xtal1 p0.0 / ad0 p0.6 / ad6 p0.7 / ad7 p0.5 / ad5 p0.4 / ad4 p0.2 / ad2 p0.3 / ad3 p1.6 / an6 / clkout p1.5 / an5 / t2ex c12 c9 c1 c3 c2 c0 r0 p4.3 / c19 p4.4 / c20 p4.5 / c21 p4.6 / c22 p5.2 / c26 p3.6 / wr p3.5 / t1 / c30 p3.3 / int1 p3.2 / int0 mcp03834 p2.4 / ad12 p2.5 / ad13 p2.6 / ad14 c4 c5 c6 c10 c11 p3.4 / t0 / c31 c505l 60 61 80 21 40 70 30 41 50 20 10 1 c15 c14 c13 r1 p1.7 / an7 / t2 p3.1 / txd p3.0 / rxd reset p4.0 / c16 p4.2 / c18 p4.1 / c17 p5.1 / c25 p5.0 / c24 c7 c8 p4.7 / c23 xtal4 23456789 13 11 12 14 15 16 17 18 19 22 23 24 25 26 27 28 29 32 39 38 37 36 35 34 33 42 43 44 45 46 47 48 49 54 59 58 56 57 55 52 53 51 62 63 64 65 66 67 68 69 79 74 78 77 76 75 73 72 71 v dd v ss p1.0 / an0 / int3 / cc0 p1.1 / an1 / int4 / cc1 p1.2 / an2 / int5 / cc2 p1.3 / an3 / int6 / cc3 p1.4 / an4 v v aref agnd p0.1 / ad1 r2 r3 p3.7 / rd p5.5 / c29 p5.4 / c28 p5.3 / c27 v v ss dd 31
c505l data sheet 5 06.99 table 1 pin definitions and functions symbol pin number i/o*) function r0-r3 1-4 1 2 3 4 o lcd row outputs output of lcd controller row lines. these pins are driven by the lcd controller and drive the row input lines of the external lcd display. enabling the lcd controller makes these pins available for lcd output levels. r0 lcd row output 0 r1 lcd row output 1 r2 lcd row output 2 r3 lcd row output 3 these pins should not be used for input. c0-c15 5-20 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 o lcd column outputs output of lcd controller column lines 0 to 15. these pins are driven by the lcd controller and drive the column input lines of the external lcd display. enabling the lcd controller makes these pins available for lcd output levels. c0 lcd column output 0 c1 lcd column output 1 c2 lcd column output 2 c3 vcclcd column output 3 c4 lcd column output 4 c5 lcd column output 5 c6 lcd column output 6 c7 lcd column output 7 c8 lcd column output 8 c9 lcd column output 9 c10 lcd column output 10 c11 lcd column output 11 c12 lcd column output 12 c13 lcd column output 13 c14 lcd column output 14 c15 lcd column output 15 these pins should not be used for input. *) i = input o = output
c505l data sheet 6 06.99 p4.0-p4.7 21-28 21 22 23 24 25 26 27 28 i/o port 4 is a 8-bit quasi-bidirectional port with internal pull-up arrangement. port 4 pins that have a 1 written to them are pulled high by the internal pull-up transistors and in that state can be used as inputs. as inputs, port 4 pins being externally pulled low will source current ( i il , in the dc characteristics) because of the internal pullup transistors. port 4 pins can also be configured as lcd column outputs. the secondary functions are assigned to the pins of port 4 as follows: p4.0 / c16 lcd column output 16 p4.1 / c17 lcd column output 17 p4.2 / c18 lcd column output 18 p4.3 / c19 lcd column output 19 p4.4 / c20 lcd column output 20 p4.5 / c21 lcd column output 21 p4.6 / c22 lcd column output 22 p4.7 / c23 lcd column output 23 these pins should not be used for input when configured as lcd output pins. p5.0-p5.5 29-34 29 30 31 32 33 34 i/o port 5 is a 6-bit quasi-bidirectional port with internal pull-up arrangement. port 5 pins that have a 1 written to them are pulled high by internal pull-up transistors and in that state can be used as inputs. as inputs, port 5 pins being externally pulled low will source current ( i il , in the dc characteristics) because of the internal pullup transistors. port 5 pins can also be configured as lcd column outputs. the secondary functions are assigned to the pins of port 5 as follows: p5.0 / c24 lcd column output 24 p5.1 / c25 lcd column output 25 p5.2 / c26 lcd column output 26 p5.3 / c27 lcd column output 27 p5.4 / c28 lcd column output 28 p5.5 / c29 lcd column output 29 these pins should not be used for input when configured as lcd output pins. *) i = input o = output table 1 pin definitions and functions (contd) symbol pin number i/o*) function
c505l data sheet 7 06.99 p3.7-p3.0 35-42 42 41 40 39 38 37 36 35 i/o port 3 is an 8-bit quasi-bidirectional port with internal pull-up arrangement. port 3 pins that have a 1 written to them are pulled high by the internal pull-up transistors and in that state can be used as inputs. as inputs, port 3 pins being externally pulled low will source current ( i il , in the dc characteristics) because of the internal pullup transistors. the output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate (except for txd and wr). p3.4 and p3.5 can also be configured as lcd column outputs c31 and c30 respectively. these pins should not be used for input when configured as lcd output pins. the secondary functions are assigned to the pins of port 3 as follows: p3.0 / rxd receiver data input (asynch.) or data input/output (synch.) of serial interface p3.1 / txd transmitter data output (asynch.) or clock output (synch.) of serial interface p3.2 / int0 external interrupt 0 input / timer 0 gate control input p3.3 / int1 external interrupt 1 input / timer 1 gate control input p3.4 / t0 / c31 timer 0 counter input / lcd column 31 output p3.5 / t1 / c30 timer 1 counter input / lcd column 30 output p3.6 / wr wr control output; latches the data byte from port 0 into the external data memory p3.7 / rd rd control output; enables the external data memory *) i = input o = output table 1 pin definitions and functions (contd) symbol pin number i/o*) function
c505l data sheet 8 06.99 reset 43 i reset a high level on this pin for two machine cycles while the oscillator is running resets the device. an internal diffused resistor to v ss permits power-on reset using only an external capacitor to v dd . psen 44 o the program store enable output is a control signal that enables the external program memory to the bus during external fetch operations. it is activated every three oscillator periods except during external data memory accesses. remains high during internal program execution. this pin should not be driven during reset operation. ale 45 o the address latch enable output is used for latching the low-byte of the address into external memory during normal operation. it is activated every three oscillator periods except during an external data memory access. when instructions are executed from internal program memory ( ea = 1), the ale generation can be disabled by bit eale in sfr syscon. this pin should not be driven during reset operation. ea 46 i external access enable this pin must be held at high level. instructions are fetched from the internal otp memory when the pc is less than 8000 h . instructions are fetched from external program memory, when the pc is greater than 7fff h . this pin must not be held at low level. *) i = input o = output table 1 pin definitions and functions (contd) symbol pin number i/o*) function
c505l data sheet 9 06.99 xtal2 47 o xtal2 output of the inverting oscillator amplifier. xtal1 48 i xtal1 input to the inverting oscillator amplifier and input to the internal clock generator circuits. to drive the device from an external clock source, xtal1 should be driven, while xtal2 is left unconnected. to operate above a frequency of 16 mhz, a duty cycle of 50% should be maintained. minimum and maximum high and low times as well as rise/ fall times specified in the ac characteristics (refer to data sheet) must be observed. xtal4 51 o xtal4 output of the inverting real-time clock oscillator amplifier. xtal3 52 i xtal3 input to the inverting real-time clock oscillator amplifier. to drive the real-time clock from an external clock source, xtal3 should be driven, while xtal4 is left unconnected. minimum and maximum high and low times as well as rise/ fall times specified in the ac characteristics (refer to data sheet) must be observed. *) i = input o = output table 1 pin definitions and functions (contd) symbol pin number i/o*) function
c505l data sheet 10 06.99 p2.7-p2.0 53-60 i/o port 2 is a an 8-bit quasi-bidirectional i/o port with internal pullup resistors. port 2 pins that have a 1 written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. as inputs, port 2 pins being externally pulled low will source current ( i il , in the dc characteristics) because of the internal pullup resistors. port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (movx @dptr). in this application it uses strong internal pullup transistors when issuing 1s. during accesses to external data memory that use 8-bit addresses (movx @ri), port 2 issues the contents of the p2 special function register and uses only the internal pullup resistors. p0.7-p0.0 61-68 i/o port 0 is an 8-bit open-drain bidirectional i/o port. port 0 pins that have a 1 written to them float, and in that state can be used as high-impendance inputs. port 0 is also the multiplexed low-order address and data bus during accesses to external program or data memory. in this application it uses strong internal pullup transistors when issuing 1s. *) i = input o = output table 1 pin definitions and functions (contd) symbol pin number i/o*) function
c505l data sheet 11 06.99 p1.0-p1.7 71-78 71 72 73 74 75 76 77 78 i/o port 1 is an 8-bit quasi-bidirectional port with internal pull-up arrangement. port 1 pins can be used for digital input/output or as analog inputs to the a/d converter. port 1 pins that have a 1 written to them are pulled high by internal pull-up transistors and in that state can be used as inputs. as inputs, port 1 pins being pulled low externally will source current ( i il , in the dc characteristics) because of the internal pullup transistors. port 1 pins are assigned to be used as analog inputs via the register p1ana. as secondary digital functions, port 1 contains the interrupt, timer, clock, capture and compare pins. the output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate (except for compare functions). the secondary functions are assigned to the pins of port 1 as follows: p1.0 / an0 / int3 / cc0 analog input channel 0 interrupt 3 input / capture/compare channel 0 i/o p1.1 / an1 / int4 / cc1 analog input channel 1/ interrupt 4 input / capture/compare channel 1 i/o p1.2 / an2 / int5 / cc2 analog input channel 2 / interrupt 5 input / capture/compare channel 2 i/o p1.3 / an3 / int6 / cc3 analog input channel 3 interrupt 6 input / capture/compare channel 3 i/o p1.4 / an4 analog input channel 4 p1.5 / an5 / t2ex analog input channel 5 / timer 2 external reload / trigger input p1.6 / an6 / clkout analog input channel 6 / system clock output p1.7 / an7 / t2 analog input channel 7 / timer/counter 2 input *) i = input o = output table 1 pin definitions and functions (contd) symbol pin number i/o*) function
c505l data sheet 12 06.99 v aref 79 C reference voltage for the a/d converter. v agnd 80 C reference ground for the a/d converter. v ss 49, 70 C ground (0 v) v dd 50, 69 C power supply (+ 5 v) *) i = input o = output table 1 pin definitions and functions (contd) symbol pin number i/o*) function
c505l data sheet 13 06.99 figure 4 block diagram of the c505l watchdog oscillator port 2 port 1 8-bit digit. i / o port 0 xram ram otp programmable watchdog timer usart generator interrupt unit 10-bit a / d converter emulation support logic port 0 port 1 port 2 port 3 port 4 osc & timing s & h xtal1 xtal2 reset ale psen ea v aref agnd v 8-bit digit. i / o / 8-bit digit. i / o mcb03835 8 datapointers cpu 256 x 8 256 x 8 32k x 8 baudrate timer 0 timer 1 timer 2 8-bit analog in clock real-time mux dd v ss v c505l 8-bit digit. i / o / 2 lcd outputs port 3 8 lcd outputs 8-bit digit. i / o / port 4 port 5 6-bit digit. i / o / 6 lcd outputs port 5 lcd controller 128-segment 20 lcd outputs xtal4 xtal3
c505l data sheet 14 06.99 cpu the c505l is efficient both as a controller and as an arithmetic processor. it has extensive facilities for binary and bcd arithmetic and excels in its bit-handling capabilities. efficient use of program memory results from an instruction set consisting of 44% one-byte, 41% two-byte, and 15% three- byte instructions. with a 16-mhz external clock, 58% of the instructions execute in 375 ns (20 mhz: 300 ns). special function register psw (address d0 h ) reset value: 00 h bit function cy carry flag used by arithmetic instruction. ac auxiliary carry flag used by instructions which execute bcd operations. f0 general purpose flag rs1 rs0 register bank select control bits these bits are used to select one of the four register banks. ov overflow flag used by arithmetic instruction. f1 general purpose flag p parity flag set/cleared by hardware after each instruction to indicate an odd/even number of one bits in the accumulator, i.e. even parity. cy ac f0 rs1 rs0 ov f1 p d0 h psw d7 h d6 h d5 h d4 h d3 h d2 h d1 h d0 h bit no. msb lsb rs1 rs0 function 0 0 bank 0 selected, data address 00 h -07 h 0 1 bank 1 selected, data address 08 h -0f h 1 0 bank 2 selected, data address 10 h -17 h 1 1 bank 3 selected, data address 18 h -1f h
c505l data sheet 15 06.99 memory organization the c505l cpu manipulates operands in the following five address spaces: C up to 64 kbytes of program memory (32k on-chip otp memory) C up to 64 kbytes of external data memory C 256 bytes of internal data memory C 256 bytes of internal xram data memory C 20 bytes of lcd controller registers C 16 bytes of real-time clock (rtc) registers C a 128-byte special function register (sfr) area figure 5 illustrates the memory address spaces of the c505l. figure 5 c505l memory map "code space" (ea = 1) internal h 0000 7fff h h 0000 "data space" data memory external external external memory 8000 h h ffff data internal lcd (36 byte) f3db h & rtc alternatively not used (256 byte) internal xram h h register function "internal data space" ram internal h 00 internal ram 80 h 7f h special mcd03996 80 h address f3dc f3ff h h address indirect h ffff ff00 h ff direct ff
c505l data sheet 16 06.99 reset and system clock the reset input is an active high input at pin reset. since the reset is synchronized internally, the reset pin must be held low for at least two machine cycles (12 oscillator periods) while the oscillator is running. a pull-down resistor is internally connected to v ss to allow a power-up reset with an external capacitor only. an automatic reset can be obtained when v dd is applied by connecting the reset pin to v dd via a capacitor. figure 6 shows the possible reset circuitries. figure 6 reset circuitries a) + b) + c505l reset c) & mcs03840 c505l c505l v dd dd v reset reset
c505l data sheet 17 06.99 figure 7 and figure 8 show the recommended oscillator circiutries for crystal and external clock operations, respectively, for the system or main clock. figure 7 recommended oscillator circuitries (for xtal1-xtal2) figure 8 recommended oscillator circuitries for real-time clock (xtal3-xtal4) xtal2 xtal1 *) to internal timing circuitry c505 c 2 c 1 *) crystal or ceramic resonator mcs03293 c505l n.c. mcs04037 xtal2 xtal1 c505l external clock signal v dd
c505l data sheet 18 06.99 multiple datapointers as a functional enhancement to the standard 8051 architecture, the c505l contains eight 16-bit datapointers instead of only one datapointer. the instruction set uses just one of these datapointers at a time. the selection of the actual datapointer is done in the special function register dpsel. figure 9 illustrates the datapointer addressing mechanism. figure 9 external data memory addressing using multiple datapointers dph(83 ) dpl(82 ) dptr0 dptr7 .0 .1 .2 - - - - - dpsel(92 ) dpsel selected data- pointer .2 .1 .0 dptr 0 0 0 0 0 0 1 dptr 1 0 1 0 dptr 2 0 1 1 dptr 3 1 0 0 dptr 4 1 0 1 dptr 5 1 1 0 dptr 6 1 1 1 dptr 7 mcd00779 external data memory h hh
c505l data sheet 19 06.99 enhanced hooks emulation concept the enhanced hooks emulation concept of the c500 microcontroller family is a new, innovative way to control the execution of c500 mcus and to gain extensive information on the internal operation of the controllers. emulation of on-chip memory based programs is possible, too. each production chip has built-in logic for the support of the enhanced hooks emulation concept. therefore, no costly bond-out chips are necessary for emulation. this also ensure that emulation and production chips are identical. the enhanced hooks technology tm 1) , which requires embedded logic in the c500 allows the c500 together with an eh-ic to function similar to a bond-out chip. this simplifies the design and reduces costs of an ice-system. ice-systems using an eh-ic and a compatible c500 are able to emulate all operating modes of the different versions of the c500 microcontrollers. this includes emulation of rom, rom with code rollover and romless modes of operation. it is also able to operate in single step mode and to read the sfrs after a break. figure 10 basic c500 mcu enhanced hooks concept configuration port 0, port 2 and some of the control lines of the c500 based mcu are used by enhanced hooks emulation concept to control the operation of the device during emulation and to transfer informations about the program execution and data transfer between the external emulation hardware (ice-system) and the c500 mcu. 1 enhanced hooks technology is a trademark and patent of metalink corporation licensed to infineon technologies. mcs02647 syscon pcon tcon reset ea psen ale port 0 port 2 i/o ports optional port 3 port 1 c500 mcu interface circuit enhanced hooks rport 0 rport 2 rtcon rpcon rsyscon tea tale tpsen eh-ic target system interface ice-system interface to emulation hardware
c505l data sheet 20 06.99 special function registers the registers, except the program counter and the four general purpose register banks, reside in the special function register area which consists of two portions: the standard special function register area and the mapped special function register area. some of the c505ls sfrs (pcon1, vr0, vr1 and vr2) are located in the mapped sfr area. for accessing the mapped sfr area, bit rmap in sfr syscon must be set. all other sfrs are located in the standard sfr area which is accessed when rmap is cleared (0). the registers and data locations of the lcd controller (lcd-sfrs) and the rtc (rtc-sfrs) are located in the external data memory area at addresses f3dd h to f3ef h and f3f0 h to f3ff h respectively. special function register syscon (address b1 h ) reset value: xx100x01 b as long as bit rmap is set, mapped sfr area can be accessed. this bit is not cleared automatically by hardware. thus, when non-mapped/mapped registers are to be accessed, the bit rmap must be cleared/set respectively by software. all sfrs with addresses where address bits 0-2 are 0 (e.g. 80 h ,88 h ,90 h ,98 h , ,f8 h ,ff h ) are bit-addressable. the 51 sfrs in the standard and mapped sfr area include pointers and registers that provide an interface between the cpu and the other on-chip peripherals. the sfrs of the c505l are listed in table 2 and table 3 .in table 2 they are organized in groups which refer to the functional blocks of the c505l. the lcd and rtc-sfrs are also included in table 2 . table 3 illustrates the contents of the sfrs in numeric order of their addresses. table 4 lists the lcd and the rtc-sfrs in numeric order of their addresses. bit function rmap sfr map bit rmap = 0: access to the non-mapped (standard) sfr area is enabled. rmap = 1: access to the mapped sfr area is enabled. C reserved bits for future use. read by cpu returns undefined values. the shaded bits are not described in this section. __ eale rmap b1 h syscon bit no. 76543210 msb lsb __ xmap1 xmap0
c505l data sheet 21 06.99 table 2 special function registers - functional blocks block symbol name address contents after reset cpu acc b dph dpl dpsel psw sp syscon 2) vr0 4) vr1 4) vr2 4) accumulator b-register data pointer, high byte data pointer, low byte data pointer select register program status word register stack pointer system control register version register 0 version register 1 version register 2 e0 h 1) f0 h 1) 83 h 82 h 92 h d0 h 1) 81 h b1 h fc h fd h fe h 00 h 00 h 00 h 00 h xxxxx000 b 3) 00 h 07 h xx10xx01 b 3) c5 h 85 h 5) a/d- converter adcon0 2) adcon1 addath addatl p1ana 2) a/d converter control register 0 a/d converter control register 1 a/d converter data register high byte a/d converter data register low byte port 1 analog input selection register d8 h 1) dc h d9 h da h 90 h 4) 00x00000 b 3) 01xxx000 b 3) 00 h 00xxxxxx b 3) ff h interrupt system ien0 2) ien1 2) ip0 2) ip1 tcon 2) t2con 2) scon 2) ircon interrupt enable register 0 interrupt enable register 1 interrupt priority register 0 interrupt priority register 1 timer control register timer 2 control register serial channel control register interrupt request control register a8 h 1) b8 h 1) a9 h b9 h 88 h 1) c8 h 1) 98 h 1) c0 h 1) 00 h 00 h 00 h xx000000 b 3) 00 h 00x00000 b 00 h 00 h xram xpage syscon 2) page address register for extended on-chip xram, lcd controller and rtc system control register 91 h b1 h 00 h xx10xx01 b 3) ports p0 p1 p1ana 2) p2 p3 p4 p5 port 0 port 1 port 1 analog input selection register port 2 port 3 port 4 port 5 80 h 1) 90 h 1) 90 h 1) 4) a0 h 1) b0 h 1) e8 h 1) f8 h 1) ff h ff h ff h ff h ff h 00 b xx111111 b 1) bit-addressable sfrs 2) this sfr is listed repeatedly since some bits of it also belong to other functional blocks. 3) x means that the value is undefined and the location is reserved 4) this sfr is a mapped sfr. for accessing this sfr, bit rmap in sfr syscon must be set. 5) the content of this sfr varies with the actual step of the c505l (e.g. 01 h for the first step)
c505l data sheet 22 06.99 serial channel adcon0 2) pcon 2) sbuf scon srell srelh a/d converter control register 0 power control register serial channel buffer register serial channel control register serial channel reload register, low byte serial channel reload register, high byte d8 h 1) 87 h 99 h 98 h 1) aa h ba h 00x00000 b 3) 00 h xx h 3) 00 h d9 h xxxxxx11 b 3) timer 0/ timer 1 tcon th0 th1 tl0 tl1 tmod timer 0/1 control register timer 0, high byte timer 1, high byte timer 0, low byte timer 1, low byte timer mode register 88 h 1) 8c h 8d h 8a h 8b h 89 h 00 h 00 h 00 h 00 h 00 h 00 h compare/ capture unit / timer 2 ccen cch1 cch2 cch3 ccl1 ccl2 ccl3 crch crcl th2 tl2 t2con ien0 2) ien1 2) comp./capture enable reg. comp./capture reg. 1, high byte comp./capture reg. 2, high byte comp./capture reg. 3, high byte comp./capture reg. 1, low byte comp./capture reg. 2, low byte comp./capture reg. 3, low byte reload register high byte reload register low byte timer 2, high byte timer 2, low byte timer 2 control register interrupt enable register 0 interrupt enable register 1 c1 h c3 h c5 h c7 h c2 h c4 h c6 h cb h ca h cd h cc h c8 h 1) a8 h 1) b8 h 1) 00 h 3) 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00x00000 b 3) 00 h 00 h watchdog wdtrel ien0 2) ien1 2) ip0 2) watchdog timer reload register interrupt enable register 0 interrupt enable register 1 interrupt priority register 0 86 h a8 h 1) b8 h 1) a9 h 00 h 00 h 00 h 00 h power save modes pcon 2) pcon1 4) power control register power control register 1 87 h 88 h 1) 00 h 0xx0xxxx b 3) 1) bit-addressable sfrs 2) this sfr is listed repeatedly since some bits of it also belong to other functional blocks. 3) x means that the value is undefined and the location is reserved 4) sfr is located in the mapped sfr area. for accessing this sfr, bit rmap in sfr syscon must be set. table 2 special function registers - functional blocks (contd) block symbol name address contents after reset
c505l data sheet 23 06.99 lcd controller dac0 lcon lcrl lcrh dign 5) d/a conversion register lcd control register lcd timer reload low register lcd timer reload high register lcd digit register n 5) f3dc h f3dd h f3de h f3df h f3en h 00 h 6) 00 h 6) 00 h 6) 00 h 6) 00 h 5) 6) real-time clock rtcon rtcr0 rtcr1 rtcr2 rtcr3 rtcr4 clreg0 clreg1 clreg2 clreg3 clreg4 rtint0 rtint1 rtint2 rtint3 rtint4 real-time clock control register real-time clock initialization register 0 real-time clock initialization register 1 real-time clock initialization register 2 real-time clock initialization register 3 real-time clock initialization register 4 clock count register 0 clock count register 1 clock count register 2 clock count register 3 clock count register 4 real-time clock interrupt register 0 real-time clock interrupt register 1 real-time clock interrupt register 2 real-time clock interrupt register 3 real-time clock interrupt register 4 f3f0 h f3f1 h f3f2 h f3f3 h f3f4 h f3f5 h f3f6 h f3f7 h f3f8 h f3f9 h f3fa h f3fb h f3fc h f3fd h f3fe h f3ff h 00 h 6) 00 h 6) 00 h 6) 00 h 6) 00 h 6) 00 h 6) 00 h 6) 00 h 6) 00 h 6) 00 h 6) 00 h 6) 00 h 6) 00 h 6) 00 h 6) 00 h 6) 00 h 6) 1) bit-addressable sfrs 2) this sfr is listed repeatedly since some bits of it also belong to other functional blocks. 3) x means that the value is undefined and the location is reserved. 4) sfr is located in the mapped sfr area. for accessing this sfr, bit rmap in sfr syscon must be set. 5) the notation n (n = 0 to f) in the lcd digit register address definition defines the number of the related lcd digit. 6) this register is located in the on-chip external data memory area. table 2 special function registers - functional blocks (contd) block symbol name address contents after reset
c505l data sheet 24 06.99 table 3 contents of the sfrs, sfrs in numeric order of their addresses addr register content after reset 1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 80 h 2) p0 ff h .7 .6 .5 .4 .3 .2 .1 .0 81 h sp 07 h .7 .6 .5 .4 .3 .2 .1 .0 82 h dpl 00 h .7 .6 .5 .4 .3 .2 .1 .0 83 h dph 00 h .7 .6 .5 .4 .3 .2 .1 .0 86 h wdtrel 00 h wdt psel .6 .5 .4 .3 .2 .1 .0 87 h pcon 00 h smod pds idls sd gf1 gf0 pde idle 88 h 2) tcon 00 h tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 88 h 3) pcon1 0xx0- xxxx b ewpd C C ws C C C C 89 h tmod 00 h gate c/ t m1 m0 gate c/ tm1 m0 8a h tl0 00 h .7 .6 .5 .4 .3 .2 .1 .0 8b h tl1 00 h .7 .6 .5 .4 .3 .2 .1 .0 8c h th0 00 h .7 .6 .5 .4 .3 .2 .1 .0 8d h th1 00 h .7 .6 .5 .4 .3 .2 .1 .0 90 h 2) p1 ff h t2 clk- out t2ex .4 int6 int5 int4 int3 90 h 3) p1ana ff h ean7 ean6 ean5 ean4 ean3 ean2 ean1 ean0 91 h xpage 00 h .7 .6 .5 .4 .3 .2 .1 .0 92 h dpsel xxxx- x000 b CCCCC.2.1.0 98 h 2) scon 00 h sm0 sm1 sm2 ren tb8 rb8 ti ri 99 h sbuf xx h .7 .6 .5 .4 .3 .2 .1 .0 a0 h 2) p2 ff h .7 .6 .5 .4 .3 .2 .1 .0 a8 h 2) ien0 00 h ea wdt et2 es et1 ex1 et0 ex0 a9 h ip0 00 h owds wdts .5 .4 .3 .2 .1 .0 aa h srell d9 h .7 .6 .5 .4 .3 .2 .1 .0 1) x means that the value is undefined and the location is reserved 2) bit-addressable sfrs 3) sfr is located in the mapped sfr area. for accessing this sfr, bit rmap in sfr syscon must be set.
c505l data sheet 25 06.99 b0 h 2) p3 ff h rd wr t1 t0 int1 int0 txd rxd b1 h syscon xx10- xx01 b C C eale rmap C C xmap1 xmap0 b8 h 2) ien1 00 h exen2 swdt ex6 ex5 ex4 ex3 eswi eadc b9 h ip1 xx00- 0000 b C C .5.4.3.2.1.0 ba h srelh xxxx- xx11 b CCCCCC.1.0 c0 h 2) ircon 00 h exf2 tf2 iex6 iex5 iex4 iex3 swi iadc c1 h ccen 00 h coca h3 cocal 3 coca h2 cocal 2 coca h1 cocal 1 coca h0 cocal 0 c2 h ccl1 00 h .7 .6 .5 .4 .3 .2 .1 .0 c3 h cch1 00 h .7 .6 .5 .4 .3 .2 .1 .0 c4 h ccl2 00 h .7 .6 .5 .4 .3 .2 .1 .0 c5 h cch2 00 h .7 .6 .5 .4 .3 .2 .1 .0 c6 h ccl3 00 h .7 .6 .5 .4 .3 .2 .1 .0 c7 h cch3 00 h .7 .6 .5 .4 .3 .2 .1 .0 c8 h 2) t2con 00x0- 0000 b t2ps i3fr C t2r1 t2r0 t2cm t2i1 t2i0 ca h crcl 00 h .7 .6 .5 .4 .3 .2 .1 .0 cb h crch 00 h .7 .6 .5 .4 .3 .2 .1 .0 cc h tl2 00 h .7 .6 .5 .4 .3 .2 .1 .0 cd h th2 00 h .7 .6 .5 .4 .3 .2 .1 .0 d0 h 2) psw 00 h cy ac f0 rs1 rs0 ov f1 p d8 h 2) adcon0 00x0- 0000 b bd clk C bsy adm mx2 mx1 mx0 d9 h addath 00 h .9 .8 .7 .6 .5 .4 .3 .2 da h addatl 00xx- xxxx b .1.0CCCCCC 1) x means that the value is undefined and the location is reserved 2) bit-addressable sfrs table 3 contents of the sfrs, sfrs in numeric order of their addresses (contd) addr register content after reset 1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
c505l data sheet 26 06.99 dc h adcon1 01xx- x000 b adcl1 adcl0 C C C mx2 mx1 mx0 e0 h 2) acc 00 h .7 .6 .5 .4 .3 .2 .1 .0 e8 h 2) p4 00 h .7 .6 .5 .4 .3 .2 .1 .0 f0 h 2) b 00 h .7 .6 .5 .4 .3 .2 .1 .0 f8 h 2) p5 xx00- 0000 h C C .5 .4 .3 .2 .1 .0 fc h 3)4) vr0 c5 h 11000101 fd h 3)4) vr1 85 h 00000101 fe h 3)4) vr2 5) .7 .6 .5 .4 .3 .2 .1 .0 1) x means that the value is undefined and the location is reserved. 2) bit-addressable sfrs. 3) sfr is located in the mapped sfr area. for accessing this sfr, bit rmap in sfr syscon must be set. 4) these are read-only registers. 5) the content of this sfr varies with the actual of the step c505l (e.g. 01 h for the first step). table 3 contents of the sfrs, sfrs in numeric order of their addresses (contd) addr register content after reset 1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
c505l data sheet 27 06.99 table 4 contents of the lcd and the rtc registers in numeric order of their addresses addr. register content after reset bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 f3dc h dac0 00 h s7 s6 s5 s4 s3 s2 s1 s0 f3dd h lcon 00 h dsb1 dsb0 0 0 0 0 csel lcen f3de h lcrl 00 h .7 .6 .5 .4 .3 .2 .1 .0 f3df h lcrh 00 h slt .14 .13 .12 .11 .10 .9 .8 f3en h dign 1) 00 h segf sega segg segb sege segc segh segd f3f0 h rtcon 00 h 0000 rtpd irtc ertc rtcs f3f1 h rtcr0 00 h .7 .6 .5 .4 .3 .2 .1 .0 f3f2 h rtcr1 00 h .7 .6 .5 .4 .3 .2 .1 .0 f3f3 h rtcr2 00 h .7 .6 .5 .4 .3 .2 .1 .0 f3f4 h rtcr3 00 h .7 .6 .5 .4 .3 .2 .1 .0 f3f5 h rtcr4 00 h .7 .6 .5 .4 .3 .2 .1 .0 f3f6 h clreg0 00 h .7 .6 .5 .4 .3 .2 .1 .0 f3f7 h clreg1 00 h .7 .6 .5 .4 .3 .2 .1 .0 f3f8 h clreg2 00 h .7 .6 .5 .4 .3 .2 .1 .0 f3f9 h clreg3 00 h .7 .6 .5 .4 .3 .2 .1 .0 f3fa h clreg4 00 h .7 .6 .5 .4 .3 .2 .1 .0 f3fb h rtint0 00 h .7 .6 .5 .4 .3 .2 .1 .0 f3fc h rtint1 00 h .7 .6 .5 .4 .3 .2 .1 .0 f3fd h rtint2 00 h .7 .6 .5 .4 .3 .2 .1 .0 f3fe h rtint3 00 h .7 .6 .5 .4 .3 .2 .1 .0 f3ff h rtint4 00 h .7 .6 .5 .4 .3 .2 .1 .0 1) the notation n (n = 0 to f) in the lcd digit register address definition defines the number of the related lcd digit.
c505l data sheet 28 06.99 digital i/o ports the c505l has five 8-bit and one 6-bit (port 5) digital i/o ports. port 0 is an open-drain bidirectional i/o port, while ports 1 through 5 are quasi-bidirectional i/o ports with internal pull-up resistors. when configured as inputs, ports 1-5 will be pulled high, and will source current when externally pulled low. port 0 will float when configured as input. the output drivers of port 0 and 2 and the input buffers of port 0 are also used for accessing external memory. in this application, port 0 outputs the low byte of the external memory address, time- multiplexed with the byte being written or read. port 2 outputs the high byte of the external memory address when the address is 16 bits wide. otherwise, the port 2 pins continue emitting the p2 special function register (sfr) contents. in this function, port 0 is not an open-drain port, but uses a strong internal pull-up. therefore, the parallel i/o ports of the c505l can be grouped into six different types which are listed in table 5 . type a and b port pins are standard c501-compatible i/o port lines, which can be used for digital i/o. the type a ports (port 0 and port 2) are also designed for accessing external data or program memory. type b port lines are located at port 3 (except p3.4 and p3.5), and are used for digital i/ o or for other alternate functions as described in the pin description. type d port lines provide the lcd controller outputs r0-r3 and c0-c15 as primary functions. type e port lines are located at port 4 and port 5 and provide the lcd controller output lines as alternate functions. type f port lines are at p3.4/t0 and p3.5/t1 and have a digital alternate input each, apart from lcd output functions. the c505l provides eight analog input lines that are implemented as mixed digital/analog inputs (type c). the 8 analog inputs, an0-an7, are located at the port 1 pins p1.0 to p1.7. after reset, all analog inputs are disabled and the related pins of port 1 are configured as digital inputs. the analog function of the specific port 1 pins are enabled by bits in the sfrs p1ana. writing a 0 to a bit position of p1ana assigns the corresponding pin to operate as analog input. note: p1ana is a mapped sfr and can only be accessed if bit rmap in sfr syscon is set. lf a digital value is to be read by port 1, the voltage levels are to be held within the input voltage specifications ( v il / v ih ). table 5 c505l port structure types type description a standard digital i/o ports which can also be used for external address/data bus. b standard multifunctional digital i/o port lines c mixed digital/analog i/o port lines with programmable analog input function d lcd output lines e standard digital i/o or lcd output lines f standard multifunctional digital i/o or lcd output lines
c505l data sheet 29 06.99 timer / counter 0 and 1 timer/counter 0 and 1 can be used in four operating modes as listed in table 6 : in the timer function (c/ t = 0) the register is incremented every machine cycle. therefore the count rate is f osc /6. in the counter function the register is incremented in response to a 1-to-0 transition at its corresponding external input pin (p3.4/t0, p3.5/t1). since it takes two machine cycles to detect a falling edge the max. count rate is f osc /12. external inputs int0 and int1 (p3.2, p3.3) can be programmed to function as a gate to facilitate pulse width measurements. figure 11 illustrates the input clock logic. figure 11 timer/counter 0 and 1 input clock logic table 6 timer/counter 0 and 1 operating modes mode description tmod input clock m1 m0 internal external (max) 0 8-bit timer/counter with a divide-by-32 prescaler 00 f osc /(6 32) f osc /(12 32) 1 16-bit timer/counter 0 1 f osc /6 f osc /12 2 8-bit timer/counter with 8-bit autoreload 1 0 3 timer/counter 0 used as one 8-bit timer/counter and one 8-bit timer timer 1 stops 11 mcs03117 1 & osc c/t = 0 c/t = 1 control =1 6 tr1 p3.5/t1 (tmod) p3.2/int0 f timer 0/1 input clock osc /6 p3.4/t0 tr0 gate p3.3/int1 _ <
c505l data sheet 30 06.99 timer/counter 2 with compare/capture/reload the timer 2 of the c505l provides additional compare/capture/reload features, which allow the selection of the following operating modes: C compare : up to 4 pwm signals with 16-bit/300 ns resolution (@ 20 mhz clock) C capture : up to 4 high speed capture inputs with 300 ns resolution C reload : modulation of timer 2 cycle time the block diagram in figure 12 shows the general configuration of timer 2 with the additional compare/capture/reload registers. the i/o pins which can used for timer 2 control are located as multifunctional port functions at port 1. figure 12 timer 2 block diagram mcb03853 comparator ccl3/cch3 capture input/ output control p1.0/ int3/ cc0 cc1 int4/ p1.1/ cc2 int5/ p1.2/ cc3 int6/ p1.3/ ccl2/cch2 comparator ccl1/cch1 comparator crcl/crch comparator bit 16 16 bit 16 bit 16 bit osc 6 12 t2ps p1.7/ t2 t2ex p1.5/ sync. & t2i1 t2i0 timer 2 th2 tl2 tf2 reload exen2 1 exf2 interrupt request compare _ < an5/ an7/ sync. pin pin reload an0/ an1/ an2/ an3/
c505l data sheet 31 06.99 timer 2 operating modes the timer 2, which is a 16-bit-wide register, can operate as timer, event counter, or gated timer. a roll-over of the count value in tl2/th2 from all 1s to all 0s sets the timer overflow flag tf2 in sfr ircon, which can generate an interrupt. the bits in register t2con are used to control the timer 2 operation. timer mode: in timer function, the count rate is derived from the oscillator frequency. a prescaler offers the possibility of selecting a count rate of 1/6 or 1/12 of the oscillator frequency. gated timer mode: in gated timer function, the external input pin t2 (p1.7) functions as a gate to the input of timer 2. lf t2 is high, the internal clock input is gated to the timer. t2 = 0 stops the counting procedure. this facilitates pulse width measurements. the external gate signal is sampled once every machine cycle. event counter mode: in the event counter function. the timer 2 is incremented in response to a 1-to-0 transition at its corresponding external input pin t2 (p1.7). in this function, the external input is sampled every machine cycle. since it takes two machine cycles (12 oscillator periods) to recognize a 1-to-0 transition, the maximum count rate is 1/6 of the oscillator frequency. there are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it must be held for at least one full machine cycle. reload of timer 2: two reload modes are selectable: in mode 0, when timer 2 rolls over from all 1s to all 0s, it not only sets tf2 but also causes the timer 2 registers to be loaded with the 16-bit value in the crc register, which is preset by software. in mode 1, a 16-bit reload from the crc register is caused by a negative transition at the correspon- ding input pin p1.5/t2ex. this transition will also set flag exf2 if bit exen2 in sfr ien1 has been set.
c505l data sheet 32 06.99 timer 2 compare modes the compare function of a timer/register combination operates as follows: the 16-bit value stored in a compare or compare/capture register is compared with the contents of the timer register; if the count value in the timer register matches the stored value, an appropriate output signal is generated at a corresponding port pin and an interrupt can be generated. compare mode 0 in compare mode 0, upon matching the timer and compare register contents, the output signal changes from low to high. lt goes back to a low level on timer overflow. as long as compare mode 0 is enabled, the appropriate output pin is controlled by the timer circuit only and writing to the port will have no effect. figure 13 shows a functional diagram of a port circuit when used in compare mode 0. the port latch is directly controlled by the timer overflow and compare match signals. the input line from the internal bus and the write-to-latch line of the port latch are disconnected when compare mode 0 is enabled. figure 13 port latch in compare mode 0 mcs02661 latch port q q clk d port pin read pin dd v read latch port circuit internal bus latch write to compare reg. compare register circuit comparator timer register timer circuit compare match s r overflow timer 16 bit bit 16
c505l data sheet 33 06.99 compare mode 1 if compare mode 1 is enabled and the software writes to the appropriate output latch at the port, the new value will not appear at the output pin until the next compare match occurs. thus, it can be choosen whether the output signal has to make a new transition (1-to-0 or 0-to-1, depending on the actual pin-level) or should keep its old value at the time when the timer value matches the stored compare value. in compare mode 1 (see figure 14 ) the port circuit consists of two separate latches. one latch (which acts as a shadow latch) can be written under software control, but its value will only be transferred to the port latch (and thus to the port pin) when a compare match occurs. figure 14 compare function in compare mode 1 timer 2 capture modes each of the compare/capture registers cc1 to cc3 and the crc register can be used to latch the current 16-bit value of the timer 2 registers tl2 and th2. two different modes are provided for this function. in mode 0, the external event causing a capture is: C for cc registers 1 to 3: a positive transition at pins cc1 to cc3 of port 1 C for the crc register: a positive or negative transition at the corresponding pin, depending on the status of the bit i3fr in sfr t2con. in mode 1 a capture occurs in response to a write instruction to the low order byte of a capture register. the write-to-register signal (e.g. write-to-crcl) is used to initiate a capture. the timer 2 contents will be latched into the appropriate capture register in the cycle following the write instruction. in this mode no interrupt request will be generated. mcs03856 latch port q q clk d read pin dd v d clk q shadow latch read latch port circuit internal bus latch write to compare reg. compare register circuit comparator timer register timer circuit compare match pin port 16 bit 16 bit
c505l data sheet 34 06.99 serial interface (usart) the serial port is full duplex and can operate in four modes (one synchronous mode, three asynchronous modes) as illustrated in table 7 . for clarification some terms regarding the difference between baud rate clock and baud rate should be mentioned. in the asynchronous modes the serial interfaces require a clock rate which is 16 times the baud rate for internal synchronization. therefore, the baud rate generators/timers have to provide a baud rate clock (output signal in figure 15 ) to the serial interface which - divided by 16 - results in the actual baud rate. further, the abbrevation f osc refers to the oscillator frequency (crystal or external clock operation). the variable baud rates for modes 1 and 3 of the serial interface can be derived either from timer 1 or from a dedicated baud rate generator (see figure 15 ). table 7 usart operating modes mode scon description sm0 sm1 0 0 0 shift register mode, fixed baud rate serial data enters and exits through r d; t d outputs the shift clock; 8-bit are transmitted/received (lsb first) 1 0 1 8-bit uart, variable baud rate 10 bits are transmitted (through t d) or received (at r d) 2 1 0 9-bit uart, fixed baud rate 11 bits are transmitted (through t d) or received (at r d) 3 1 1 9-bit uart, variable baud rate like mode 2
c505l data sheet 35 06.99 figure 15 block diagram of baud rate generation for the serial interface table 8 below lists the values/formulas for the baud rate calculation of the serial interface with its dependencies of the control bits bd and smod. table 8 serial interface - baud rate dependencies serial interface operating modes active control bits baud rate calculation bd smod mode 0 (shift register) C C f osc / 6 mode 1 (8-bit uart) mode 3 (9-bit uart) 0 x controlled by timer 1 overflow: (2 smod timer 1 overflow rate) / 32 1 x controlled by baud rate generator (2 smod f osc ) / (32 baud rate generator overflow rate) mode 2 (9-bit uart) C 0 1 f osc / 32 f osc / 16 mcs02733 rate f osc (smod) baud clock pcon.7 2 (sm0/ sm1) scon.7 scon.6 only one mode can be selected adcon0.7 (bd) 0 1 0 1 baud rate generator (srelh srell) timer 1 mode 2 mode 0 note: the switch configuration shows the reset state. mode 3 mode 1 overflow 6
c505l data sheet 36 06.99 lcd controller unit the liquid crystal display (lcd) controller unit in the c505l is designed for the control of an lcd display module of 128 display segments (4 rows and 32 columns) using the 1/4 duty-cycle driving method. the c505l can be programmed to generate reference voltages for adjusting the contrast of the display. an example of a typical lcd module is shown in figure 16 . the table describes the different combinations of the row and column signals required to activate a particular segment. the signals r0-r3 and c0-c31 are the row and column signals, respectively, connected to the display module. figure 16 organization of a typical lcd display module the memory required by the lcd controller includes a control register, lcon, the d/a converter register dac0 and 16 individual digit registers (digx, x = 0 to f). these registers are implemented in the on-chip external data memory area. accesses to these registers are similar to on-chip xram accesses (movx instructions) and therefore must be preceded by an enable operation on the on- chip xram. note: the actual segment organization within the display unit could be different from the example considered here. in such cases, the segment names/positions may vary. the user should consult the manufacturer of the lcd display unit used regarding its segment organization. the lcd outputs of the c505l must work at a frequency which is not more than 360 hz in order to activate a display segment. to achieve this 360-hz frequency limit, the lcd controller uses a scheme as shown in figure 17 . a g fb ec d h r2 r3 r1 r0 c1 c0 rows columns c1 c0 r3 fa r2 g b r1 e c r0 dh mcd03858
c505l data sheet 37 06.99 . figure 17 lcd clocking the generated lcd clock has a duty-cycle of 50%. the table in figure 17 shows the recommended reload values at different input frequencies ( f lcdin ) to generate lcd clocks of frequencies less than 360 hz. the frequency of the lcd clock could be calculated by: mcd03859 1 0 rtc f osc f csel slt lcdin f 15-bit down counter lc14-0 lcr14 lcr0 lcr14-0 lc0 lc14 underflow (reload) toggle lcd f (< 360 hz) lcr (15-bit reload) lcd f (in hz) lcdin f 32.768 khz 002e h 356.17 2 mhz 0ada h 359.97 4 mhz 15b4 h 359.97 6 mhz 208e h 359.97 20 mhz 16 mhz 12 mhz 10 mhz 6c84 h 3642 56d0 411c h h h 359.97 359.97 359.97 359.97 f lcd = f lcdin 2 (15-bit reload value) hz
c505l data sheet 38 06.99 display voltage levels the lcd controller outputs three voltage levels required for driving the lcd display module. these voltage levels are generated by a programmable 8-bit d/a converter via the register dac0 and a resistive divider network. the d/a converter is enabled by the lcd controller enable bit lcen (lcon.0). any write operation to the register dac0 with the lcd controller enabled, starts the d/a conversion and thereby the display outputs. therefore, the c505l can be used with a wide range of lcd display modules. lcd controller in power saving mode in order to reduce power consumption, the c505l can be put into the software power down mode 2. in this mode, the lcd controller and the d/a converter do not lose their register contents and remain in operation, provided the following conditions are satisfied: C the input clock to the lcd is the 32.768 khz real-time clock input, and C the real-time clock input at xtal3 and xtal4 pins is still valid.
c505l data sheet 39 06.99 real-time clock the real-time clock unit of the c505l contains a dedicated oscillator and a 47-bit timer which is used to count time elapsed with respect to an initial time. the c505l real-time clock does not provide for any error correction. any such corrections can be done by software only. functionality the real-time clock can be initialized to a 40-bit initial value, which are loaded into the upper 40-bits of the timer. the lower 7 bits of the counter are never accessible by the user and merely act as prescalers that are initialized to 0000000 b after a start operation on the real-time clock. one increment of the clock register is made for every cycle of the input clock (32.768 khz). the functionality of the real-time clock is shown in figure 18 . figure 18 real-time clock the register memory for the real-time clock is implemented in the on-chip external data memory area. accesses to these registers are similar to on-chip xram accesses (movx instructions) and therefore must be preceded by an enable operation on the on-chip xram. these registers include the rtcon, rtcr0 to rtcr4 (rtcr), clreg0 to clreg4 (clreg) and rtint0 to rtint4 (rtint) registers. control ertc rtint, 40-bit register 40-bit comparator clreg, 40-bit timer rtcr, 40-bit register mcs03865 lsb msb bit 0 bit 6 osc. irtc 32.768 khz input these bits are not readable. wake - up request rtcs 7-bit timer
c505l data sheet 40 06.99 real-time clock in power saving modes once started in the normal mode, the oscillator as well as the whole real-time clock could remain in operation during certain power-down modes where the power supply could be reduced to a minimum of 3v . these are the power down modes 2 and 3, where other functional units of the c505l are powered down ( see power saving modes on page 50. ). the upper 40-bit content of the real-time clock counter can be compared with the content of the programmable rtint register in order to generate an interrupt request while the c505l is in one of software power-down modes 2 or 3, provided all of the following conditions are fulfilled: C the c505l is in one of the software power-down modes 2 or 3, C wake-up from software power-down is enabled (bit ewpd = 1 in sfr pcon1) C real-time clock wake-up source is selected (bit ws = 1 in sfr pcon1), C the real-time clock interrupt is enabled (bit ertc = 1 of rtcon), and C normally operating v dd levels are maintained in this case, the handling is similar to the wake-up from power-down through p3.2/ int0.
c505l data sheet 41 06.99 10-bit a/d converter the c505l includes a high performance / high speed 10-bit a/d-converter (adc) with 8 analog input channels. it operates with a successive approximation technique and uses self calibration mechanisms for reduction and compensation of offset and linearity errors. the a/d converter provides the following features: C 8 multiplexed input channels (port 1), which can also be used as digital inputs/outputs C 10-bit resolution C single or continuous conversion mode C internal start-of-conversion trigger capability C interrupt request generation after each conversion C using successive approximation conversion technique via a capacitor array C built-in hidden calibration of offset and linearity errors the 10-bit adc uses two clock signals for operation: the conversion clock f adc (= 1/ t adc ) and the input clock f in (= 1/ t in ). f adc is derived from the c505l system clock f osc which is applied at the xtal pins. the input clock f in is equal to f osc the conversion f adc clock is limited to a maximum frequency of 2 mhz. therefore, the adc clock prescaler must be programmed to a value which assures that the conversion clock does not exceed 2 mhz. the prescaler ratio is selected by the bits adcl1 and adcl0 of sfr adcon1. figure 19 10-bit a/d converter clock selection mcs03867 32 16 8 4 mux adcl0 adcl1 osc f clock prescaler conversion clock f adc input clock in f a/d converter conditions: f adc max = 2 mhz f in = f osc = 1 clp mcu system clock rate ( f osc ) f in [mhz] prescaler ratio f adc [mhz] adcl1 adcl0 2 mhz 2 ? 4 0.5 0 0 6 mhz 6 ? 4 1.5 0 0 8 mhz 8 ? 4200 12 mhz 12 ? 8 1.5 0 1 16 mhz 16 ? 8201 20 mhz 20 ? 16 1.25 1 0
c505l data sheet 42 06.99 figure 20 block diagram of the 10-bit a/d converter eadc iadc ean7 ean4 ean5 ean6 ean3 ean2 ean1 ean0 adcl1 mx2 mx1 mx0 adcon1 (dc ) p1ana (90 ) ircon (c0 ) ien1 (b8 ) h h h h bsy adm mx2 mx1 mx0 adcon0 (d8 ) h mux s&h single / continuous mode clock prescaler 32, 16, 8, 4 f osc port 1 .2 .3 .4 .5 .6 .7 .8 lsb msb .1 addatl (da ) addath (d9 ) hh conversion clock input clock adc f in f aref v agnd v start of conversion write to addatl shaded bit locations are not used in adc - functions. internal bus a / d mcb03866 internal bus bd clk exf2 exen2 swdt iex6 iex5 iex4 iex3 swi converter adcl2 ex6 swdt esw1 tf2 exen2 ex5 ex4 ex3
c505l data sheet 43 06.99 interrupt system the c505l provides 12 interrupt vectors with four priority levels. five interrupt requests can be generated by the on-chip peripherals (timer 0, timer 1, timer 2, serial interface, a/d converter) and six interrupts may be triggered externally (p3.2/ int0, p3.3/ int1, p1.0/an0/ int3/cc0, p1.1/an1/ int4/cc1, p1.2/an2/int5/cc2, p1.3/an3/int6/cc3). additionally, the p1.5/an5/t2ex can trigger an interrupt. there is one software-generated interrupt (bit swi in sfr ien1) in addition to the above interrupts. the wake-up from power-down mode interrupt has a special functionality which allows an exit from the software power-down mode by a short low pulse at either pin p3.2/ int0 or by the real-time clock interrupt. figure 21 to figure 23 give a general overview of the interrupt sources and illustrate the corresponding request and the control flags. table 9 lists all interrupt sources with the corresponding request flags and interrupt vector addresses. table 9 interrupt source and vectors interrupt source interrupt vector address interrupt request flags external interrupt 0 0003 h ie0 timer 0 overflow 000b h tf0 external interrupt 1 0013 h ie1 timer 1 overflow 001b h tf1 serial channel 0023 h ri / ti timer 2 overflow / ext. reload 002b h tf2 / exf2 a/d converter 0043 h iadc software interrupt 004b h swi external interrupt 3 0053 h iex3 external interrupt 4 005b h iex4 external interrupt 5 0063 h iex5 external interrupt 6 006b h iex6 wake-up from power-down mode 007b h irtc (real-time clock wake-up only)
c505l data sheet 44 06.99 figure 21 interrupt structure, overview part 1 ea et0 ip1.1 ip0.1 iadc eadc ex0 ip1.0 ip0.0 ie0 ien0.0 tcon.1 0003 h h 0043 h 000b h 004b ien1.0 ircon.0 ien1.1 ien0.1 a / d converter ien0.7 highest priority level lowest priority level p o l l i n g s e q u e n c e mcb03869 it0 tcon.5 tf0 tcon.0 p3.2 / int0 overflow timer 0 bit addressable request flag is cleared by hardware ircon.1 eswi swi software interrupt
c505l data sheet 45 06.99 figure 22 interrupt structure, overview part 2 ea et1 iex3 ex3 ex1 ip1.2 ip0.2 ie1 ien0.2 tcon.3 0013 h h 0053 h 001b h 005b ien1.2 ircon.2 ien1.3 ien0.3 ien0.7 highest priority level lowest priority level p o l l i n g s e q u e n c e mcb03304 it1 tcon.7 tf1 tcon.2 p3.3 / int1 overflow timer 1 bit addressable request flag is cleared by hardware an0 / int3 / t2con.6 i3fr p1.0 / cc0 ip0.3 ip1.3 ircon.3 iex4 an1 / p1.1 / int4 / cc1 ex4
c505l data sheet 46 06.99 figure 23 interrupt structure, overview part 3 ea et2 iex5 ex5 es ip1.4 ip0.4 ri ien0.4 scon.0 0023 h h 0063 h 002b h 006b ien1.4 ircon.4 ien1.5 ien0.5 ien0.7 highest priority level lowest priority level p o l l i n g s e q u e n c e mcb03305 usart overflow timer 2 bit addressable request flag is cleared by hardware ip0.5 ip1.5 ircon.5 iex6 an2 / p1.2 / int5 / cc2 ex6 ti scon.1 >1 cc3 int6 / p1.3 / ircon.7 exf2 tf2 ircon.6 >1 ien1.7 exen2 an5 / t2ex p1.5 /
c505l data sheet 47 06.99 fail save mechanisms the c505l offers enhanced fail safe mechanisms, which allow an automatic recovery from software upset or hardware failure: C a programmable watchdog timer (wdt), with variable time-out period from 192 m supto approx. 393.2 ms at 16 mhz (314.5 ms at 20 mhz). C an oscillator watchdog (owd) which monitors the on-chip oscillator and forces the microcontroller into reset state in case the on-chip oscillator fails; it also provides the clock for a fast internal reset after power-on. the watchdog timer in the c505l is a 15-bit timer, which is incremented by a count rate of f osc /12 up to f osc /192. the system clock of the c505l is divided by two prescalers, a divide-by-two and a divide-by-16 prescaler. for programming of the watchdog timer overflow rate, the upper 7 bits of the watchdog timer can be written. figure 24 shows the block diagram of the watchdog timer unit. figure 24 block diagram of the watchdog timer the watchdog timer can be started by software (bit swdt in sfr ien1) but it cannot be stopped during active mode of the device. if the software fails to refresh the running watchdog timer an internal reset will be initiated on watchdog timer overflow. for refreshing of the watchdog timer the content of the sfr wdtrel is transferred to the upper 7-bit of the watchdog timer. the refresh sequence consists of two consecutive instructions which set the bits wdt and swdt each. the reset cause (external reset or reset caused by the watchdog) can be examined by software (flag wdts). it must be noted, however, that the watchdog timer is halted during the idle mode and power down mode of the processor. mcb03306 ip0 (a9 ) h osc f wdts 2 16 14 07 8 wdtl wdth / 6 external hw reset control logic ien0 (a8 ) h ien1 (b8 ) h 6 70 wdt reset - request wdtpsel wdtrel (86 ) h wdt swdt owds
c505l data sheet 48 06.99 oscillator watchdog the oscillator watchdog unit serves for four functions: C monitoring of the on-chip oscillators function the watchdog supervises the on-chip oscillators frequency; if it is lower than the frequency of the auxiliary rc oscillator in the watchdog unit, the internal clock is supplied by the rc oscillator and the device is brought into reset; if the failure condition disappears (i.e. the on- chip oscillator has a higher frequency than the rc oscillator), the part executes a final reset phase of typ. 1 ms in order to allow the oscillator to stabilize; then the oscillator watchdog reset is released and the part starts program execution again. C fast internal reset after power-on the oscillator watchdog unit provides a clock supply for the reset before the on-chip oscillator has started. the oscillator watchdog unit also works identically to the monitoring function. C control of wake-up from software power-down mode when the software power-down mode is left by a low level at the p3.2/ int0 pin or an active real-time clock interrupt request flag irtc, the oscillator watchdog unit assures that the microcontroller resumes operation (execution of the power-down wake-up interrupt) with the nominal clock rate. in the power-down mode the rc oscillator and the on-chip oscillator are stopped. both oscillators are started again when power-down mode is released. when the on- chip oscillator has a higher frequency than the rc oscillator, the microcontroller starts operation after a final delay of typ. 1 ms in order to allow the on-chip oscillator to stabilize. note: the oscillator watchdog unit is always enabled.
c505l data sheet 49 06.99 figure 25 block diagram of the oscillator watchdog int. clock xtal1 xtal2 owds mcb03870 ip0 (a9 ) h 3 mhz f rc delay 1 f 2 f 2 f 1 f < irtc start / stop start / stop mode activated power - down power - down mode wake - up interrupt internal reset 10 p3.2 / int0 control ws (rtcon.2) ewpd >1 frequency comparator rc on-chip oscillator logic oscillator logic control (pcon1.0)
c505l data sheet 50 06.99 power saving modes the c505l provides three basic power saving modes, the idle mode, the slow-down mode and the software power down mode. C idle mode the cpu is gated off from the oscillator. all peripherals are still provided with the clock and are able to work. idle mode is entered by software and can be left by an interrupt or reset. C slow down mode the controller remains fully functional, but its normal clock frequency is internally divided by 32. this slows down all parts of the controller, the cpu and all peripherals, to 1/32 of their normal operating frequency and also reduces power consumption. C software power down modes: software power-down mode 1 , in which all the peripheral blocks and the cpu are stopped. this mode is used to save contents of internal ram, xram and sfrs with a very low standby current. software power-down mode 2 , in which only the real-time clock and lcd controller are operating. in this mode, the cpu and the rest of the peripherals are stopped. the rc oscillator and the on-chip oscillator are stopped, the real-time clock oscillator that operates with the xtal3 and xtal4 pins is still running and the real-time count is maintained in this mode. software power-down mode 3 , in which only the real-time clock is operating. in this mode, the clock input into the cpu, lcd controller and the rest of the peripherals are stopped. the only difference between this mode and mode 2 is that the lcd controller is also stopped in this mode. in all the software power-down modes, v dd can be reduced to minimize power consumption. in the case of the software power-down mode 3, v dd can be reduced to 3v (lower specification limit). it must be ensured, however, that v dd is not reduced before any of the power-down modes is invoked, and that v dd is restored to its normal operating level before leaving the power-down mode. any of these software power-down modes can be exited either by an active reset signal or by a wake-up request. using reset to leave power-down mode puts the microcontroller with its sfrs into the reset state. program execution then starts from the address 0000 h . using a wake-up request to exit the power-down mode starts the rc oscillator and the on-chip oscillator and maintains the state of the sfrs, which were frozen when power-down mode was entered. when the c505l is in software power-down mode 1, a wake-up operation is possible only through p3.2/ int0. there are two ways to use a wake-up request to exit power-down modes 2 and 3: C wake-up via p3.2/ int0 pin, or C wake-up via the real-time clock interrupt
c505l data sheet 51 06.99 table 10 power saving modes overview mode entering sequence example leaving by remarks idle mode orl pcon, #01h orl pcon, #20h occurrence of an interrupt from a peripheral unit cpu clock is stopped; cpu maintains their data; peripheral units are active (if enabled) and provided with clock hardware reset slow down mode in normal mode: orl pcon, #10h anl pcon,#0efh internal clock rate is reduced to 1/32 of its nominal frequency hardware reset with idle mode: orl pcon, #01h orl pcon, #30h occurrence of an interrupt from a peripheral unit cpu clock is stopped; cpu maintains their data; peripheral units are active (if enabled) and provided with 1/32 of its nominal frequency hardware reset software power down mode1 ... bit lcen (lcon register) is cleared; bit rtpd (rtcon register) is set; orl pcon, #02h orl pcon, #40h short low pulse at pin p3.2/ int0 oscillator is stopped; contents of on-chip ram, xram and sfrs are maintained; hardware reset software power down mode 2 ... bits lcen and csel (lcon register) are set, bit rtpd (rtcon register) is cleared; ... orl pcon, #02h orl pcon, #40h short low pulse at pin p3.2/ int0 or real-time clock wake-up interrupt oscillator is stopped; contents of on-chip ram, xram and sfrs are maintained; lcd controller and real-time clock are functioning hardware reset software power down mode 3 ... bit lcen (lcon register) is cleared; bit rtpd (rtcon register) is cleared; ... orl pcon, #02h orl pcon, #40h short low pulse at pin p3.2/ int0 or real-time clock wake-up interrupt oscillator is stopped; contents of on-chip ram, xram and sfrs are maintained; real-time clock is functioning hardware reset
c505l data sheet 52 06.99 otp memory operation the c505l contains a 32 kbyte one-time programmable (otp) program memory. with the c505l fast programming cycles are achieved (1 byte in 100 m s). also several levels of otp memory protection can be selected. for programming of the device, the c505l must be put into the programming mode. this typically is done not in-system but in a special programming hardware. in the programming mode the c505l operates as a slave device similar as an eprom stand-alone memory device and must be controlled with address/data information, control lines, and an external 11.5 v programming voltage. figure 26 shows the pins of the c505l which are required for controlling of the otp programming mode. figure 26 programming mode configuration mcl04038 c505l p0.0-7 xtal1 xtal2 v dd v ss ea/ v pp prog prd reset psen psel pmsel1 pmsel0 pale p2.0-7 port 2 port 0
c505l data sheet 53 06.99 pin configuration in programming mode figure 27 p-mqfp-80 pin configuration of the c505l in programming mode (top view) n.c. n.c. n.c. n.c. mcp03877 n.c. n.c. n.c. n.c. n.c. c505l 60 61 80 21 40 70 30 41 50 20 10 1 n.c. n.c. n.c. n.c. 515 25 35 45 55 65 75 n.c. n.c. n.c. n.c. n.c. n.c. d0 d3 n.c. n.c. n.c. n.c. n.c. n.c. n.c. d4 d2 d6 d7 d5 d1 n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. prd psel pale dd ss v v a1 / a9 a3 / a11 a2 / a10 n.c. prog psen xtal2 ea / xtal1 a5 / a13 a6 / a14 pmsel0 reset v ss pmsel1 dd v a4 / a12 a7 a0 / a8 n.c. pp v p - mqfp - 80 package
c505l data sheet 54 06.99 table 11 is a functional description of all c505l pins that are required for otp memory programming. table 11 pin definitions and functions of the c505l in programming mode symbol pin number i/o *) function p-mqfp-80 reset 43 i reset this input must be at static 1 (active) level during the whole programming mode. pmsel0 pmsel1 42 41 i i programming mode selection pins these pins are used to select the different access modes in programming mode. pmsel1,0 must satisfy a setup time to the rising edge of pale. when the logic level of pmsel1,0 is changed, pale must be at low level. psel 40 i basic programming mode select this input is used for the basic programming mode selection and must be switched according to figure 28 . prd 39 i programming mode read strobe this input is used for read access control for otp memory read, version byte read, and lock-bit read operations. pale 38 i programming address latch enable pale is used to latch the high address lines. the high address lines must satisfy a setup and hold time to/from the falling edge of pale. pale must be at a low level when the logic level of pmsel1,0 is changed. xtal2 47 o xtal2 output of the inverting oscillator amplifier. xtal1 48 i xtal1 input to the oscillator amplifier. *) i = input o = output pmsel1 pmsel0 access mode 0 0 reserved 0 1 read signature bytes 1 0 program/read lock-bits 1 1 program/read otp memory byte
c505l data sheet 55 06.99 v ss 49, 70 C circuit ground potential must be applied in programming mode. v dd 50, 69 C power supply terminal must be applied in programming mode. a0-a7, a8-a14 (port 2) 60-53 i address lines multiplexed address input lines a0-a7 and a8-a14. a8-a14 must be latched with pale. psen 44 i program store enable this input must be at static 0 level during the whole programming mode. prog 45 i programming mode write strobe this input is used in programming mode as a write strobe for otp memory program, and lock-bit write operations. during basic programming mode selection a low level must be applied to prog. ea/ v pp 46 C programming voltage this pin must be at 11.5 v ( v pp ) voltage level during programming of an otp memory byte or lock-bit. during an otp memory read operation, this pin must be at v ih high level. this pin is also used for basic programming mode selection. at basic programming mode selection a low level must be applied to ea/ v pp . d7-d0 (port 0) 68-61 i/o data lines 0-7 during programming mode, data bytes are transferred via the bidirectional d7-d0 lines that are located at port 0 pins. n.c. 1-37, 51-52, 71-80 C not connected these pins should not be connected in programming mode. *) i = input o = output table 11 pin definitions and functions of the c505l in programming mode (contd) symbol pin number i/o *) function p-mqfp-80
c505l data sheet 56 06.99 basic programming mode selection the basic programming mode selection scheme is shown in figure 28 . figure 28 basic programming mode selection clock (xtal1 / xtal2) reset psen pmsel1,0 prog prd psel pale ea / v pp v dd 5 v v pp ih2 v "1" "0" 0,1 "0" "1" "0" 0 v ready for access mode selection during this period signals are not actively driven mcs03878 stable
c505l data sheet 57 06.99 lock bits programming / read the c505l has two programmable lock-bits that, when programmed according to table 13 , provide four levels of protection for the on-chip otp code memory. note: a 1 means that the lock-bit is not programmed. a 0 means that lock-bit is programmed. table 12 access modes selection access mode ea/ v pp prog prd pmsel address (port 2) data (port 0) 10 program otp memory byte v pp h h h a0-7 a8-14 d0-7 read otp memory byte v ih h program otp lock bits v pp h h l C d1,d0 see table 13 read otp lock bits v ih h read otp version byte v ih h l h byte addr. of sign. byte d0-7 table 13 lock bit protection types lock bits at d1,d0 protection level protection type d1 d0 1 1 level 0 the otp lock feature is disabled. during normal operation of the c505l, the state of the ea pin is not latched on reset. 1 0 level 1 during normal operation of the c505l, movc instructions executed from external program memory are prevented from fetching code bytes from internal memory. ea is sampled and latched on reset. an otp memory read operation is only possible in the otp verification mode. further programming of the otp memory is disabled (reprogramming security). 0 1 level 2 same as level 1, but otp memory read operation using otp verification mode is disabled. 0 0 level 3 same as level 2, but external code execution by setting ea = low during normal operation of the c505l is not possible. external code execution, which is initiated by an internal program (e.g. by an internal jump instruction above the otp memory boundary), is still possible.
c505l data sheet 58 06.99 note: future steppings of c505l would have a different version byte 2 content. version bytes the steppings of the c505l versions will contain the following version register/byte information: stepping version byte 0 = vr0 (mapped addr. fc h ) version byte 1 = vr1 (mapped addr. fd h ) version byte 2 = vr2 (mapped addr. fe h ) c505l ca-step c5 h 85 h 04 h
c505l data sheet 59 06.99 note: stresses above those listed under absolute maximum ratings may cause permanent damage of the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for longer periods may affect device reliability. during absolute maximum rating overload conditions ( v in > v dd or v in < v ss ) the voltage on v dd pins with respect to ground ( v ss ) must not exceed the values defined by the absolute maximum ratings. absolute maximum ratings parameter symbol limit values unit notes min. max. storage temperature t st C 40 150 cC voltage on v dd pins with respect to ground ( v ss ) v dd C 0.5 6.5 v C voltage on any pin with respect to ground ( v ss ) v in C 0.5 v dd + 0.5 v C input current on any pin during overload condition - C10 10 ma C absolute sum of all input currents during overload condition -- | 100 ma | ma C power dissipation p diss - 1wC
c505l data sheet 60 06.99 operating conditions parameter symbol limit values unit notes min. max. supply voltage (normal mode) v dd 4.25 5.5 v C supply voltage (software power down mode 3 only) 3 v not during wake-up sequence. ground voltage v ss 0vC ambient temperature sab-c505l saf-c505l sak-c505l t a t a t a 0 C40 C40 70 85 125 cC analog reference voltage v aref 4 v dd + 0.1 v C analog ground voltage v agnd v ss C 0.1 v ss + 0.2 v C analog input voltage v ain v agnd v aref vC cpu clock f cpu 2 20 mhz C
c505l data sheet 61 06.99 notes see page 63 . dc characteristics (operating conditions apply) parameter symbol limit values unit test condition min. max. input low voltages all except ea, reset, xtal3 ea pin reset pin xtal3 v il v il1 v il2 v il3 C 0.5 C 0.5 C 0.5 C 0.5 0.2 v dd C 0.1 0.2 v dd C 0.3 0.2 v dd + 0.1 0.7 v dd v v v v C C C C input high voltages except xtal1, reset, xtal3 and ea xtal1 reset, ea xtal3 v ih v ih1 v ih2 v ih3 0.2 v dd + 0.9 0.7 v dd 0.6 v dd 0.9 v dd v dd + 0.5 v dd + 0.5 v dd + 0.5 v dd + 0.5 v v v v C C C C output low voltages ports 1, 2, 3, 4, 5 port 0, ale, psen v ol v ol1 C C 0.45 0.45 v v i ol = 1.6 ma 1) i ol = 3.2 ma 1) output high voltages ports 1, 2, 3, 4, 5 port 0 in external bus mode, ale, psen v oh v oh2 2.4 0.9 v dd 2.4 0.9 v dd C C C C v v v v i oh =C80 m a i oh =C10 m a i oh = C 800 m a 2) i oh =C80 m a 2) logic 0 input current ports 1, 2, 3, 4, 5 i il C10 C70 m a v in = 0.45 v logical 0-to-1 transition current ports 1, 2, 3, 4, 5 i tl C 65 C 650 m a v in =2v input leakage current port 0, an0-7(port 1), ea i li C 1 m a 0.45 < v in < v dd pin capacitance c io C10pf f c = 1 mhz, t a =25 c overload current i ov C 5ma 8) 9) programming voltage v pp 10.9 12.1 v 11.5 v 5% 12) supply current at ea/ v pp CC 30 ma 12)
c505l data sheet 62 06.99 notes see next page. power supply current (operating conditions apply) parameter symbol limit values unit test condition typ. 10) max. 11) active mode 16 mhz 20 mhz i dd i dd 28.7 34.0 36.6 43.0 ma 4) idle mode 16 mhz 20 mhz i dd i dd 13.7 15.9 19.4 22.0 ma 5) active mode with slow-down enabled 16 mhz 20 mhz i dd i dd 5.7 6.2 7.6 8.1 ma 6) idle mode with slow-down enabled 16 mhz 20 mhz i dd i dd 4.7 4.9 7.5 8.0 ma 7) power down current: software power-down mode 1 software power-down mode 2 software power-down mode 3 i pd1 i pd2 i pd3 20 250 20 50 300 50 m a m a m a v dd =2 ? 5.5 v 3) v dd = 4.25 - 5.5 v 3) v dd =3 ? 5.5 v 3)
c505l data sheet 63 06.99 notes: 1) capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the v ol of ale and port 3. the noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operation. in the worst case (capacitive loading > 100 pf), the noise pulse on ale line may exceed 0.8 v. in such cases it may be desirable to qualify ale with a schmitt-trigger, or use an address latch with a schmitt-trigger strobe input. 2) capacitive loading on ports 0 and 2 may cause the v oh on ale and psen to momentarily fall below the 0.9 v dd specification when the address lines are stabilizing. 3) power-down modes: i pd1 is measured under following conditions: e a=port 0= v dd ; reset = v ss .; xtal2 = xtal4 = n.c.; xtal1 = xtal3 = v ss ; v agnd = v ss ; v aref = v dd ; all other pins are disconnected. conditions for i pd2 and i pd3 are similar except that xtal3 and xtal4 have a valid input from the 32.768 khz crystal and the power supply limits. 4) i dd (active mode) is measured with: xtal1 driven with t r / t f = 5 ns, 50% duty cycle , v il = v ss +0.5v, v ih = v dd C 0.5 v; xtal2 = n.c.; ea = port0 = reset = v dd ; all other pins are disconnected. i dd would be slightly higher if a crystal oscillator is used (approx. 1 ma) 5) i dd (idle mode) is measured with all output pins disconnected and with all peripherals disabled; xtal1 driven with t r / t f = 5 ns, 50% duty cycle, v il = v ss + 0.5 v, v ih = v dd C 0.5 v; xtal2 = n.c.; reset = ea = v ss ; port0 = v dd ; all other pins are disconnected; the microcontroller is put into idle mode by software; 6) i dd (active mode with slow-down) is measured with all output pins disconnected and with all peripherals disabled; xtal1 driven with t r / t f = 5 ns, 50% duty cycle, v il = v ss + 0.5 v, v ih = v dd C 0.5 v; xtal2 = n.c.; reset = e a= v ss ; all other pins are disconnected; the microcontroller is put into slow-down mode by software; 7) i dd (idle mode with slow-down) is measured with all output pins disconnected and with all peripherals disabled; xtal1 driven with t r / t f = 5 ns, 50% duty cycle, v il = v ss + 0.5 v, v ih = v dd C 0.5 v; xtal2 = n.c.; reset = ea = v ss ; port0 = v dd ; all other pins are disconnected; the microcontroller is put into idle mode with slow-down enabled by software; 8) overload conditions under operating conditions occur if the voltage on the respective pin exceeds the specified operating range (i.e. v ov > v dd + 0.5v or v ov < v ss C 0.5v). the absolute sum of input overload currents on all port pins may not exceed 50 ma . the supply voltage ( v dd and v ss ) must remain within the specified limits. 9) not 100% tested, guaranteed by design characterization 10) the typical i dd values are periodically measured at t a = + 25 c but not 100% tested. 11) the maximum i dd values are measured under worst case conditions ( t a = 0 c or C 40 c and v dd = 5.5 v) 12) only valid in programming mode.
c505l data sheet 64 06.99 figure 29 i dd diagram note: 1. f osc is the oscillator frequency in mhz. i dd values are given in ma. 2. i dd graph for idle mode with slow-down enabled is not shown since it is very similar to active mode with slow-down enabled. table 14 power supply current calculation formulas parameter symbol formula active mode i dd typ i dd max 1.33 f osc + 7.33 1.61 f osc + 10.8 idle mode i dd typ i dd max 0.54 f osc + 5.07 0.66 f osc + 8.83 active mode with slow-down enabled i dd typ i dd max 0.12 f osc + 3.87 0.12 f osc + 5.77 idle mode with slow-down enabled i dd typ i dd max 0.05 f osc + 3.9 0.12 f osc + 5.67 mcd04040 0 0 f osc dd i mhz ma dd typ i i dd max 4 8 12 16 20 10 20 30 40 50 active mode active mode idle mode idle mode slow down mode slow down mode
c505l data sheet 65 06.99 note: 1) conditions as in v o apply. lcd-output characteristics (operating conditions apply) parameter symbol limit values unit test condition min. typ. max. full range output voltage, of d/a converter v o 0 - 4.75 7% v v normal mode v dd range (operating conditions) settling time of d/a converter output t set -- 350 s v dd = 5 v dc differential non-linearity of d/a converter dnl -- 1 lsb - dc integral non-linearity of d/a converter inl -- 6% v dd = 5 v dc offset voltage of d/a converter --- 15 mv - lcd voltage levels v lcd1 v lcd2 v lcd3 - v o 2 v o /3 v o /3 - v 1)
c505l data sheet 66 06.99 notes see next page. further timing conditions: t adc min = 500 ns t in = 1 / f osc = t clp a/d converter characteristics (operating conditions apply) parameter symbol limit values unit test condition min. max. analog input voltage v ain v agnd v aref v 1) sample time t s C64 t in 32 t in 16 t in 8 t in ns prescaler ? 32 prescaler ? 16 prescaler ? 8 prescaler ? 4 2) conversion cycle time t adcc C 384 t in 192 t in 96 t in 48 t in ns prescaler ? 32 prescaler ? 16 prescaler ? 8 prescaler ? 4 3) total unadjusted error t ue C 2 lsb v ss + 0.5 v v ain v dd C 0.5 v 4) C 4 lsb v ss < v ain < v dd + 0.5 v v dd C 0.5 v < v ain < v dd 4) internal resistance of reference voltage source r aref C t adc / 250 C 0.25 k w t adc in [ns] 5) 6) internal resistance of analog source r asrc C t s / 500 C 0.25 k w t s in [ns] 2) 6) clock calculation table: clock prescaler ratio adcl1, 0 t adc t s t adcc ? 32 1 1 32 t in 64 t in 384 t in ? 16 1 0 16 t in 32 t in 192 t in ? 8 0 1 8 t in 16 t in 96 t in ? 4 0 0 4 t in 8 t in 48 t in
c505l data sheet 67 06.99 notes: 1) v ain may exceed v agnd or v aref up to the absolute maximum ratings. however, the conversion result in these cases will be x000 h or x3ff h , respectively. 2) during the sample time the input capacitance c ain must be charged/discharged by the external source. the internal resistance of the analog source must allow the capacitance to reach their final voltage level within t s . after the end of the sample time t s , changes of the analog input voltage have no effect on the conversion result. 3) this parameter includes the sample time t s , the time for determining the digital result and the time for the calibration. values for the conversion clock t adc depend on programming and can be taken from the table on the previous page. 4) t ue is tested at v aref = 5.0 v, v agnd =0v, v dd = 4.9 v. it is guaranteed by design characterization for all other voltages within the defined voltage range. if an overload condition occurs on maximum 2 unused analog input pins and the absolute sum of input overload currents on all analog input pins does not exceed 10 ma, an additional conversion error of 1/2 lsb is permissible. 5) during the conversion the adcs capacitance must be repeatedly charged or discharged. the internal resistance of the reference source must allow the capacitance to reach their final voltage level within the indicated time. the maximum internal resistance results from the programmed conversion timing. 6) not 100% tested, but guaranteed by design characterization.
c505l data sheet 68 06.99 ac characteristics (16 mhz, 0.4 to 0.6 duty cycle) (operating conditions apply) ( c l for port 0, ale and psen outputs = 100 pf; c l for all other outputs = 80 pf) *) interfacing the c505l to devices with float times up to 20 ns is permissible. this limited bus contention will not cause any damage to port 0 drivers. program memory characteristics parameter symbol limit values unit 16-mhz clock duty cycle 0.4 to 0.6 variable clock 1/clp= 2 mhz to 16 mhz min. max. min. max. ale pulse width t lhll 48 C clp C 15 C ns address setup to ale t avll 10 C tcl hmin C15 C ns address hold after ale t llax 10 C tcl hmin C 15 C ns ale to valid instruction in t lliv C 75 C 2 clp C 50 ns ale to psen t llpl 10 C tcl lmin C15 C ns psen pulse width t plph 73 C clp+ tcl hmin C15 Cns psen to valid instruction in t pliv C 38 C clp + tcl hmin C 50 ns input instruction hold after psen t pxix 0C0 C ns input instruction float after psen t pxiz *) C 15 C tcl lmin C10 ns address valid after psen t pxav *) 20 C tcl lmin C 5 C ns address to valid instruction in t aviv C 95 C 2 clp + tcl hmin C55 ns address float to psen t azpl C5 C C5 C ns
c505l data sheet 69 06.99 ac characteristics (16 mhz, 0.4 to 0.6 duty cycle) (contd) external data memory characteristics parameter symbol limit values unit 16-mhz clock duty cycle 0.4 to 0.6 variable clock 1/clp= 2 mhz to 16 mhz min. max. min. max. rd pulse width t rlrh 158 C 3 clp C 30 C ns wr pulse width t wlwh 158 C 3 clp C 30 C ns address hold after ale t llax2 48 C clp C 15 C ns rd to valid data in t rldv C 100 C 2 clp + tcl hmin C 50 ns data hold after rd t rhdx 0C0 C ns data float after rd t rhdz C 51 C clp C 12 ns ale to valid data in t lldv C 200 C 4 clp C 50 ns address to valid data in t avdv C 200 C 4 clp + tcl hmin C 75 ns ale to wr or rd t llwl 73 103 clp + tcl lmin C 15 clp+ tcl lmin + 15 ns address valid to wr t avwl 95 C 2 clp C 30 C ns wr or rd high to ale high t whlh 10 40 tcl hmin C 15 tcl hmin + 15 ns data valid to wr transition t qvwx 5 C tcl lmin C 20 C ns data setup before wr t qvwh 163 C 3 clp + tcl lmin C 50 Cns data hold after wr t whqx 5 C tcl hmin C 20 C ns address float after rd t rlaz C0C 0 ns
c505l data sheet 70 06.99 ac characteristics (16 mhz, 0.4 to 0.6 duty cycle) (contd) note: the 16 mhz values in the tables are given as an example for a typical duty cycle variation of the oscillator clock from 0.4 to 0.6. external clock drive characteristics parameter symbol cpu clock = 16 mhz duty cycle 0.4 to 0.6 variable cpu clock 1/clp = 2 to 16 mhz unit min. max. min. max. oscillator period clp 62.5 62.5 62.5 500 ns high time tcl h 25 C 25 clp C tcl l ns low time tcl l 25 C 25 clp C tcl h ns rise time t r C 10 C 10 ns fall time t f C 10 C 10 ns oscillator duty cycle dc 0.4 0.6 25 / clp 1 C 25 / clp C clock cycle tcl 25 37.5 clp dc min clp dc max ns
c505l data sheet 71 06.99 ac characteristics (20 mhz, 0.5 duty cycle) (operating conditions apply) c l for port 0, ale and psen outputs = 100 pf; c l for all other outputs = 80 pf) *) interfacing the c505l to devices with float times up to 20 ns is permissible. this limited bus contention will not cause any damage to port 0 drivers. program memory characteristics parameter symbol limit values unit 20 mhz clock 0.5 duty cycle variable clock 1/clp = 2 mhz to 20 mhz min. max. min. max. ale pulse width t lhll 35 C clp C 15 C ns address setup to ale t avll 10 C clp/2 C 15 C ns address hold after ale t llax 10 C clp/2 C 15 C ns ale to valid instruction in t lliv C 55 C 2 clp C 45 ns ale to psen t llpl 10 C clp/2 C 15 C ns psen pulse width t plph 60 C 3/2 clp C 15 Cns psen to valid instruction in t pliv C 25 C 3/2 clp C 50 ns input instruction hold after psen t pxix 0C0 C ns input instruction float after psen t pxiz *) C 20 C clp/2 C 5 ns address valid after psen t pxav *) 20 C clp/2 C 5 C ns address to valid instruction in t aviv C 65 C 5/2 clp C 60 ns address float to psen t azpl C 5 C C 5 C ns
c505l data sheet 72 06.99 ac characteristics (20 mhz, 0.5 duty cycle) (contd) external data memory characteristics parameter symbol limit values unit 20 mhz clock 0.5 duty cycle variable clock 1/clp = 2 mhz to 20 mhz min. max. min. max. rd pulse width t rlrh 120 C 3 clp C 30 C ns wr pulse width t wlwh 120 C 3 clp C 30 C ns address hold after ale t llax2 35 C clp C 15 C ns rd to valid data in t rldv C 75 C 5/2 clpC 50 ns data hold after rd t rhdx 0C0Cns data float after rd t rhdz C 38 C clp C 12 ns ale to valid data in t lldv C 150 C 4 clp C 50 ns address to valid data in t avdv C 150 C 9/2 clp C 75 ns ale to wr or rd t llwl 60 90 3/2 clp C 15 3/2 clp + 15 ns address valid to wr t avwl 70 C 2 clp C 30 C ns wr or rd high to ale high t whlh 10 40 clp/2 C 15 clp/2 + 15 ns data valid to wr transition t qvwx 5 C clp/2 C 20 C ns data setup before wr t qvwh 125 C 7/2 clp C 50 C ns data hold after wr t whqx 5 C clp/2 C 20 C ns address float after rd t rlaz C0C0ns external clock drive characteristics parameter symbol limit values unit variable clock freq. = 2 mhz to 20 mhz min. max. oscillator period clp 50 500 ns high time tcl h 15 clp C tcl l ns low time tcl l 15 clp C tcl h ns rise time t r C10ns fall time t f C10ns oscillator duty cycle dc 0.5 0.5 C
c505l data sheet 73 06.99 figure 30 program memory read cycle mct00096 ale psen port 2 lhll t a8 - a15 a8 - a15 a0 - a7 instr.in a0 - a7 port 0 t avll plph t t llpl t lliv t pliv t azpl t llax t pxiz t pxix t aviv t pxav
c505l data sheet 74 06.99 figure 31 data memory read cycle mct00097 ale psen port 2 whlh t port 0 rd t lldv t rlrh t llwl t rldv t avll t llax2 t rlaz t avwl t avdv t rhdx t rhdz a0 - a7 from ri or dpl from pcl a0 - a7 instr. in data in a8 - a15 from pch p2.0 - p2.7 or a8 - a15 from dph
c505l data sheet 75 06.99 figure 32 data memory write cycle figure 33 external clock drive on xtal1 mct00098 ale psen port 2 whlh t port 0 wr t wlwh t llwl t qvwx t avll t llax2 t qvwh t avwl t whqx a0 - a7 from ri or dpl from pcl a0 - a7 instr.in data out a8 - a15 from pch p2.0 - p2.7 or a8 - a15 from dph tcl h tcl l clp t r t f 0.2 v dd 0.7 dd v - 0.1 mct03310 xtal1
c505l data sheet 76 06.99 ac characteristics of programming mode v dd = 5 v 10 %; v pp = 11.5 v 5 %; t a = 25 c 10 c parameter symbol limit values unit min. max. pale pulse width t paw 35 C ns pmsel setup to pale rising edge t pms 10 C C address setup to pale, prog, or prd falling edge t pas 10 C ns address hold after pale, prog, or prd falling edge t pah 10 C ns address, data setup to prog or prd t pcs 100 C ns address, data hold after prog or prd t pch 0Cns pmsel setup to prog or prd t pms 10 C ns pmsel hold after prog or prd t pmh 10 C ns prog pulse width t pww 100 C m s prd pulse width t prw 100 C ns address to valid data out t pad C75ns prd to valid data out t prd C20ns data hold after prd t pdh 0Cns data float after prd t pdf C20ns prog high between two consecutive prog low pulses t pwh1 1C m s prd high between two consecutive prd low pulses t pwh2 100 C ns xtal clock period t clkp 83.3 500 ns
c505l data sheet 77 06.99 figure 34 programming code byte - write cycle timing t paw t pms pah t pas t a8-a14 a0-a7 d0-d7 pcs t pww t pch t t pwh mct03642 h, h pale pmsel1,0 port 2 port 0 prog notes: prd must be high during a programming write cycle.
c505l data sheet 78 06.99 figure 35 verify code byte - read cycle timing t paw t pms pah t pas t a8-a14 a0-a7 pad t d0-d7 t pdh t pdf prd t pcs t prw t pch t t pwh mct03643 h, h pale pmsel1,0 port 2 port 0 prd prog must be high during a programming read cycle. notes:
c505l data sheet 79 06.99 figure 36 lock bit access timing figure 37 version byte read timing h, l h, l d0, d1 d0, d1 t pcs pms t pmh t t pch pww t pms t prd t t pdh pdf t pmh t prw t mct03644 pmsel1,0 port 0 prog prd pale should be low during a lock bit read / write cycle. note: e. g. fd d0-7 t pcs pms t t pdh pdf t pmh t mct03645 port 2 port 0 prd pmsel1,0 l, h h prw t prd t pch t prog must be high during a programming read cycle. note:
c505l data sheet 80 06.99 figure 38 otp verification mode note: this mode cannot be entered if otp protection levels of 1 to 3 are programmed. otp verification mode characteristics note: ale pin described below is the pin 45. parameter symbol limit values unit min. typ. max. ale pulse width t awd C clp C ns ale period t acy C 6 clp C ns data valid after ale t dva C C 2 clp ns data stable after ale t dsa 4 clp C C ns p3.5 setup to ale low t as C tcl h Cns oscillator frequency 1/ clp 4C6mhz mct02613 t acy t awd t dsa dva t t as data valid ale port 0 p3.5
c505l data sheet 81 06.99 figure 39 ac testing: input, output waveforms figure 40 ac testing: float waveforms figure 41 recommended oscillator circuits for crystal oscillator at xtal1 0.45 v v dd 0.2 -0.1 +0.9 0.2 dd v test points mct00039 v dd -0.5 v ac inputs during testing are driven at v dd C 0.5 v for a logic 1 and 0.45 v for a logic 0. timing measurements are made at v ihmin for a logic 1 and v ilmax for a logic 0. mct00038 v load v load -0.1 v +0.1 v load v timing reference points v oh -0.1 v +0.1 v ol v for timing purposes a port pin is no longer floating when a 100 mv change from load voltage occurs and begins to float when a 100 mv change from the loaded v oh / v ol level occurs. i ol / i oh 3 20 ma mcs03311 c 2 - 20 mhz xtal2 xtal1 xtal1 xtal2 n.c. external oscillator signal crystal oscillator mode driving from external source crystal mode: c = 20 pf 10 pf (incl. stray capacitance) c
c505l data sheet 82 06.99 figure 42 recommended oscillator circuits for real-time clock oscillator at xtal3 the recommended oscillator circuitry for the real-time clock oscillator configuration using a crystal oscillator of 32.768 khz. mcs04039 xtal4 xtal3 xtal3 xtal4 crystal oscillator mode driving from external source external oscillator signal n.c. 32.768 mhz = 68 pf; crystal mode : 4 c 3 c 3 c = 33 or 48 pf c 4
c505l data sheet 83 06.99 figure 43 p-mqfp-80-1 package outline 0.65 0.3 12.35 0.1 2 2.45 max 1 80 index marking 17.2 14 0.25 min +0.1 0.88 1) 0.6x45? 1) does not include plastic or metal protrusions of 0.25 max per side a-b 0.2 h d 4x a-b 0.2 d 80x a b d c 0.12 80x d a-b m c 1) 14 17.2 -0.05 h 7?max -0.02 +0.08 0.15 0.08 gpm05249 plastic package, p-mqfp-80-1 (smd) (plastic metric quad flat pack) sorts of packing package outlines for tubes, trays etc. are contained in our data book package information dimensions in mm smd = surface mounted device

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